Linux on a CVA6, and SMP firmware on a €30 module. Both on real silicon.

Two platforms, one ladder. An application-class core running a real Linux userspace, and a microcontroller-class SoC running real SMP firmware. Both validated on physical hardware — and the RTL underneath both is open and auditable.

Why it is different

1. Silicon, not a promise. Each claim ships with its evidence: UART log, console capture, checksum, timing report. The numbers above come off the board, not out of a model — and the one figure that is not clean is printed alongside the ones that are.
2. A gated, reproducible flow. Cycle-accurate co-simulation → bitstream (timing, resource and sha256 gates) → physical silicon. Testbenches have a mutation mode, because a test that cannot fail proves nothing. A pre-flight lint catches bugs invisible in simulation — it intercepted a dual-driver signal that Vivado's DRC rejected.
3. A cheap way in. The microcontroller-class proof runs on a €30–50 module and a JTAG dongle. No proprietary development board, no expensive tool licence — and the same engineering discipline on both platforms.
4. Ready for heterogeneous compute. Both tiers already expose mapped accelerator and DMA slots, and cross-core coherency is validated on the small one: the "CPU + accelerator on the same fabric" brick is in place.

Where it stands

The platform targets the buyers that closed silicon excludes or overcharges: European research groups, integrators under GDPR and AI Act pressure, and anyone who needs a datapath they can actually read.

Two things that never meet in commercial silicon are combined here. A software-recompilable RISC-V core gives an open, auditable instruction path and no vendor lock-in — and it is already proven up to a Linux userspace on a plain soft-core. A systolic-array NPU built on FPGA fabric will give a datapath that survives model changes by recompiling — instead of a silicon respin or a new part number. Underneath both sits HBM2 bandwidth that most competing small accelerators simply do not have.

The design posture is deliberate about what this is not:

• Not a GPU competitor. On raw TOPS/$ and TOPS/W, dedicated edge-AI parts win, and any claim otherwise is marketing.
• Not a commodity edge-AI part. Camera-tile inference in volume belongs to Hailo and Axelera.
• Not a cloud service. It is a card and a toolchain, on your bench or in your rack.

What it wins on is the combination those alternatives cannot offer: an auditable open RTL path, a reconfigurable datapath, HBM-class bandwidth in a 75 W half-height card, and a provenance that stands up to a procurement filter written as "no third-country-controlled supplier".

Working notes, dated when the work lands — or labelled by the gate it closes. Threads still running are marked open.

1. 2026-08-31

   Market and positioning study

   Four verticals scored on sales friction and willingness to pay. Conclusion: lead with academic and R&D prototyping, keep edge AI and defence behind it, do not attack the data centre. Positioning fixed as CVA6-first.

2. 2026-09-01

   HBM FPGA sourcing audit

   Every FPGA with on-package HBM2/HBM2e compared on bandwidth, LUT count, price and lifecycle status. Alveo U50 selected as the scale-up reference: best bandwidth per watt per euro in the 2026 market.

3. 2026-09-05

   Prototyping cost model

   AWS F2 (VU47P) against a local U50 for the bring-up phase: compile, simulation and hardware-in-the-loop budgets. Result — the cloud path costs less than the electricity and cooling argument for a local card, until sustained bandwidth testing starts.

4. open

   The CVA6 kernel still arrives over UART

   11 MB takes about 17 minutes at 115,200 baud — tolerable for bring-up, unusable for iteration. The same SD-boot approach now proven on the Ibex platform is the fix.

5. G3

   Standalone boot — FSBL in the Boot ROM

   A 4,130-byte bare-metal FSBL lives in BRAM and boots the payload itself: BRAM → SD card → validate → jump. The host programmed the FPGA and streamed nothing. Validation is mandatory before the jump — magic, length, checksum — and hart 1 is released via MSIP[1] only once it passes.

6. G4

   It boots on its own now

   The 16 MiB configuration flash was backed up first — full image, hash taken — then written, then verified by a real power-cycle with nothing else attached. The FPGA configures from its own flash. That closes the chain end to end: RTL → SD card → filesystem → second stage → Boot ROM → flash. Seven gates, none skipped.

7. next

   Multiboot with a golden image

   An image header protects against corruption, not against a bad update. Multiboot lets the FPGA fall back to a known-good image by itself — documented, not yet implemented.

Email camille@systolic-labs.com copy

I am one engineer. If the scope is real, I will tell you what I can deliver and what I cannot — that conversation takes less time than a proposal.